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邮箱：eesyang@ustc.tsg211.com
办公室：杨树，教授，博士生导师。主要从事宽禁带半导体功率器件设计、微纳制造及可靠性研究。自主研制出1kV/1.1mΩ·cm2单极型和1.8kV/0.5mΩ·cm2双极型垂直GaN器件，功率品质因数国际较为领先；研制出国际上首个无电流崩塌的新型垂直GaN器件，克服了长期困扰GaN器件的动态性能退化难题；提出了针对GaN器件的氮化界面层结构，有效抑制介质/GaN界面陷阱、提升器件可靠性。主持国家自然科学基金面上项目和青年项目、国家重点研发计划课题、教育部联合基金、浙江省杰出青年科学基金、台达电力电子重点项目、功率半导体企业委托项目等。在IEEE EDL、IEEE T-PEL和功率半导体领域国际会议IEEE ISPSD、IEEE IEDM等发表SCI/EI论文80余篇。担任IEEE EDS Power Devices and ICs技术委员会委员，功率半导体领域顶级会议IEEE ISPSD技术委员会委员（2019~2023），中国电源学会女科学家工作委员会副主任委员，Elsevier Power Electronic Devices and Components联合主编，IEEE JESTPE客座编委。
2006-2010 复旦大学，学士，微电子学
2010-2014 香港科技大学，博士，电子及计算机工程
2014-2016 香港科技大学，客座助理教授
2016-2016 剑桥大学，博士后
2016-2022 浙江大学，百人计划研究员
2018 IEEE ISPSD Charitat Young Researcher Award（全球每年1~2位青年学者，该奖项创立30年来首位中国大陆获奖者）
2022 达摩院青橙奖
2022 MIT Technology Review亚太区35岁以下科技创新35人
2020 中国电源学会科学技术奖-优秀青年奖
2020 中达青年学者奖
2021 电源领域最美科技工作者
2016 首届CASA第三代半导体卓越创新青年
2015 香港科技大学SENG PhD Research Excellence Award
(invited) S. Yang*, S. Han, et al., “Dynamic on-resistance in GaN power devices: Mechanisms, characterizations and modeling,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 7, no. 3, pp. 1425-1439, Sep. 2019.
S. Han, S. Yang*, et al., “Current-collapse-free and fast reverse recovery performance in vertical GaN-on-GaN Schottky barrier diode,” IEEE Trans. Power Electron., vol. 36, no. 6., pp. 5012-5018, Jun. 2019. (Featured in Compound Semiconductor and Semiconductor Today)
S. Han, S. Yang*, et al., “Conductivity modulation in vertical GaN PiN diode: Evidence and impact,” IEEE Electron Device Lett., vol. 42, no. 3, pp. 300-303, Mar. 2021. (Featured in Compound Semiconductor)
S. Han, S. Yang*, et al., “High-voltage and high-ION/IOFF vertical GaN-on-GaN Schottky barrier diode with nitridation-based termination,” IEEE Electron Device Lett., vol. 39, no. 4, pp. 572–575, Apr. 2018. (Featured in Compound Semiconductor and Semiconductor Today)
S. Han, S. Yang*, et al., “Fluorine-implanted termination for vertical GaN Schottky rectifier with high blocking voltage and low forward voltage drop,” IEEE Electron Device Lett., vol. 40, no. 7, pp. 1040–1043, Jul. 2019.
Y. Liu, S. Yang*, et al., “Investigation of surge current capability of GaN E-HEMTs in the third quadrant: The impact of p-GaN contact,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 7, no. 3, pp. 1465-1474, Sep. 2019.
S. Yang*, C. Zhou, et al., “Impact of substrate bias polarity on buffer-related current collapse in AlGaN/GaN-on-Si power devices,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 5048–5056, Dec. 2017.
S. Yang*, Z. Tang, et al., “High-quality interface in Al2O3 /GaN/AlGaN/GaN MIS-structures with in situ pre-gate plasma nitridation,” IEEE Electron Device Lett., vol. 34, no. 12, pp. 1497–1499, Dec. 2013. (ESI Highly Cited Paper)
S. Yang*, S. Liu, et al., “AC-capacitance techniques for interface trap analysis in GaN-based buried-channel MIS-HEMTs,” IEEE Trans. Electron Devices, vol. 62, no. 6, pp. 1870–1878, June 2015.
S. Yang*, Y. Lu, et al., “Dynamic gate stress-induced VTH shift and its impact on dynamic RON in GaN MIS-HEMTs,” IEEE Electron Device Lett., vol. 37, no. 2, pp. 157–160, Feb. 2016.
